World's First Sub 1nm Chip Fits 100 Billion Transistors Into Fingernail Size

IBM has introduced what it describes as the world’s first chip technology below 1 nanometer, designed to fit nearly 100 billion transistors onto a die roughly the size of a fingernail.

The new technology nearly doubles the transistor density of IBM’s experimental 2nm chip, which the company first demonstrated in 2021. The smallest and most advanced chips currently contain around 80 billion transistors.

NanoStack Design

The technology is based on NanoStack, a three-dimensional transistor architecture that stacks and staggers complementary metal-oxide-semiconductor devices vertically along the z-axis.

IBM previously developed the nanosheet transistor designs now being adopted by major chip manufacturers at the 3nm and 2nm process nodes.

However, NanoStack goes further by joining two nanosheet transistors into one vertical structure. IBM can optimize each transistor layer independently and connect the two devices from opposite sides.

Each transistor in the demonstrated structure contains three nanosheets measuring less than 5nm in thickness, or roughly 15 silicon atoms across. Spacers measuring about 9nm separate the nanosheets.

IBM then bonds two of these transistor devices vertically using an extremely thin dielectric process, which the company described as one of the technology’s main innovations.

Different Materials

The upper and lower transistors can use different channel materials, metals and dielectric materials.

IBM therefore describes NanoStack as a transistor platform rather than a single manufacturing technique. The company believes it can continue developing the design through several generations, including 7 angstrom, 5 angstrom, 3 angstrom and potentially 1 angstrom technologies.

One angstrom equals one ten-billionth of a meter, while 10 angstroms equal one nanometer.

Jay Gambetta, director of IBM Research and an IBM Fellow, said the company was not simply reducing transistor sizes but changing how chips are built to improve performance and energy efficiency.

Performance Gains

Based on IBM’s internal comparisons with its 2nm technology, NanoStack could provide up to 50% higher performance while consuming the same amount of power.

Alternatively, it could reduce power consumption by as much as 70% while delivering the same level of performance.

IBM’s vice president of silicon technology research and development, Huiming Bu, similarly said the technology could improve performance by 50% compared with the best chips currently available while reducing power use by 70%.

Improved Memory Density

IBM also reported a 40% improvement in the scaling of static random-access memory cell area compared with its 2nm technology.

The company described the improvement as a step the semiconductor industry has not achieved in more than a decade.

The increase could be especially important for artificial intelligence accelerators, which rely heavily on on-chip memory capacity and bandwidth.

Greater SRAM density could allow chip designers to place larger caches and more on-die memory closer to processing units. This could reduce the amount of data that needs to move across the chip during AI training and inference tasks.

Three-Dimensional Scaling

Bu described NanoStack as a new approach that moves chip scaling fully into three dimensions.

He said the technology could give the semiconductor industry at least another decade of progress as manufacturing moves from nanometer-scale processes into the angstrom era.

Instead of only making transistors smaller across a flat surface, the system increases density by arranging devices vertically.